Patent Document 1 discloses a method of improving the covering completeness of a barrier film by attaching a polymer film onto a porous dielectric film surface by a hydrocarbon plasma treatment.
In the method disclosed in Patent Document 1, first, as shown in FIG. 5(a), an etching-stop diffusion-barrier film 103 is formed on an underlayer film 101 having an interconnect 102 on a semiconductor substrate. The etching-stop diffusion-barrier film is typically a silicon nitride film (Si3N4) or a silicon carbide film (SiC). Then, a porous dielectric layer 104 having a low dielectric constant is formed. Thereafter, a via 107 and a trench 108 are formed by etching with use of a photoresist mask. After the mask is removed by asking, the via penetrates through the porous dielectric layer 104 and the etching-stop diffusion-barrier film 103 to reach the interconnect 102, and the trench is provided with a cross-sectional shape having a depth of about ½ of the film thickness of the porous dielectric layer 104 (FIG. 5(b)).
Then, the hydrocarbon gas plasma treatment is carried out to attach a thin polymer film 109c onto the interlayer insulating film surface and onto the surface of the interconnect exposed at the bottom part of the via 107 (FIG. 5(c)). The polymer film 109c is formed under a pressure of 7 to 60 mTorr and with a power of 500 to 1700 W by using a C2H4 gas.
After forming a TaN film 110 having a Cu barrier property and a power-feeding Cu film at the time of Cu plating by the PVD method, a Cu film 111 is buried into the via 107 and the trench 108 by the plating method (FIG. 6(a)). Then, by CMP, the Cu film 111, the TaN film 110, and the polymer film 109c on the porous dielectric layer top surface are successively removed, so as to form an interconnect (FIG. 6(b)).
Also, Patent Document 2 discloses the following method.
First, as shown in FIG. 7(a), an etching-stop diffusion-barrier film 103 is formed on an underlayer film 101 having an interconnect 102 on a semiconductor substrate. Then, a via 107 and a trench 108 are formed by a predetermined method in a porous dielectric layer 104 having a low dielectric constant (FIG. 7(b)).
Then, a polymer film 109c is attached onto the side wall of the via 107 and the trench 108 and onto the utmost surface of the substrate by CVD or the application method. Subsequently, by anisotropic plasma etching, the polymer film 109c is allowed to remain on the side surface of the via 107 and the trench 108 (FIG. 7(c)).
After forming a TaN film 110 having a Cu barrier property and a power-feeding Cu film at the time of Cu plating by the PVD method, a Cu film 111 is buried into the via 107 and the trench 108 by the plating method (FIG. 8(a)). Then, by CMP, the Cu film 111, the TaN film 110, and the polymer film 109c on the porous dielectric layer top surface are successively removed, so as to form an interconnect (FIG. 8(b)).